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CY7C1618KV18 Datenblatt (PDF) - Cypress Semiconductor

CY7C1618KV18 Datasheet PDF - Cypress Semiconductor
Teilenummer CY7C1618KV18
Download  CY7C1618KV18 Download

Filegröße   753.0 Kbytes
Page   32 Pages
Hersteller  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor
Bauteilbeschribung 144-Mbit DDR II SRAM Two-Word Burst Architecture

CY7C1618KV18 Datasheet (PDF)

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CY7C1618KV18 Datasheet PDF - Cypress Semiconductor

Teilenummer CY7C1618KV18
Download  CY7C1618KV18 Click to download

Filegröße   753.0 Kbytes
Page   32 Pages
Hersteller  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor
Bauteilbeschribung 144-Mbit DDR II SRAM Two-Word Burst Architecture

CY7C1618KV18 Datenblatt (HTML) - Cypress Semiconductor

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CY7C1618KV18 Produktdetails

Functional Description
The CY7C1618KV18, and CY7C1620KV18 are 1.8-V synchronous pipelined SRAM equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. On CY7C1618KV18 and CY7C1620KV18, the burst counter takes in the least significant bit of the external address and bursts two 18-bit words in the case of CY7C1618KV18 and two 36-bit words in the case of CY7C1620KV18 sequentially into or out of the device.

Features
■ 144-Mbit density (8M × 18, 4M × 36)
■ 333 MHz clock for high bandwidth
■ Two-word burst for reducing address bus frequency
■ Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz
■ Two input clocks (K and K) for precise DDR timing
   ❐ SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high-speed systems
■ Synchronous internally self-timed writes
■ DDR II operates with 1.5-cycle read latency when DOFF is asserted high
■ Operates similar to DDR I device with one cycle read latency when DOFF is asserted low
■ 1.8-V core power supply with high-speed transceiver logic (HSTL) inputs and outputs
■ Variable drive HSTL output buffers
■ Expanded HSTL output voltage (1.4 V–VDD)
   ❐ Supports both 1.5-V and 1.8-V I/O supply
■ Available in 165-ball fine-pitch ball grid array (FBGA) package (15 × 17 × 1.4 mm)
■ Offered in Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Phase locked loop (PLL) for accurate data placement




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Über Cypress Semiconductor


Cypress Semiconductor ist ein amerikanisches Unternehmen, das sich auf das Design und die Herstellung von digitalen und analogen integrierten Hochleistungsschaltungen (ICs) spezialisiert hat.
Das Unternehmen wurde 1982 gegründet und hat seinen Hauptsitz in San Jose, Kalifornien, USA.
Cypress bietet eine breite Palette von Produkten, darunter Mikrocontroller, Speicherprodukte, drahtlose Konnektivitätslösungen und andere digitale und analoge ICs.
Die Produkte des Unternehmens werden in verschiedenen Anwendungen wie Unterhaltungselektronik, Automobilsystemen, Industriesystemen und vielem mehr verwendet.
Cypress ist bekannt für sein Fachwissen in der Mischsignal- und programmierbaren System-auf-A-Chip-Technologie (PSOC), hochwertige Produkte und Innovationen im Bereich eingebetteter Systeme.

*Diese Informationen dienen nur zu allgemeinen Informationszwecken. Wir haften nicht für Verluste oder Schäden, die durch die oben genannten Informationen verursacht werden.




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