# CD4028B-Series Logic Gate Datasheet Summary

## Packaging Information
️· Available Packages: PDIP, CDIP, SOIC, SO, NS, TSSOP, and Plastic Small-Outline Packages
️· Package Suffixes: E, F3A, M, M96, MT, NSR, PW, PWR
️· Quantity: Varies by package (e.g., 16, 40, 250, 2000, 90)

## Product Status Definitions
️· ACTIVE: Recommended for new designs.
️· LIFEBUY: Discontinued, lifetime-buy period in effect.
️· NRND: Not recommended for new designs; supports existing customers.
️· PREVIEW: Not in production; samples may/may not be available.
️· OBSOLETE: Discontinued production.

## Environmental/Compliance Information
️· Lead (Pb-Free): Compatible with RoHS requirements (lead ≤ 0.1% by weight).
️· Green (RoHS & no Sb/Br): Lead-free and halogen-free (bromine/antimony ≤ 0.1%).

## Moisture Sensitivity Level
️· Based on JEDEC standard classifications and peak solder temperature.

## Mechanical Data
️· Plastic Small-Outline Package (PW): Drawings and dimensions provided. 14 pins shown for illustration.
️· Dimensions in millimeters.
️· Complies with JEDEC MO-153.

## Important Notice/Disclaimer
️· Texas Instruments (TI) reserves the right to modify products/services.
️· TI’s liability is limited to the purchase price of the parts.
️· TI provides no warranty for customer product design.
️· Information on third-party products does not constitute an endorsement.