STM32WLE4JC datasheet(107/145 Pages) STMICROELECTRONICS

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DS13105 Rev 8

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STM32WLE5/E4xx

Electrical characteristics

133

5.3.14

Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is

stressed to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 s) are applied to

the pins of each sample according to each pin combination. The sample size depends on

the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to

the ANSI/JEDEC standard.

Static latch-up

The following complementary static tests are required on three parts to assess the latch-up

performance:

•

A supply overvoltage is applied to each power supply pin.

•

A current injection is applied to each input, output and configurable I/O pin.

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Table 68. EMI characteristics

Symbol

Parameter

Conditions

Monitored

frequency band

Peripheral ON

SMPS OFF

fHSE = /fCPUM4, fCPUM0]

Unit

fHSE = 32 MHz

fCPU = 48 MHz

SEMI

Peak level

VDD = 3.6 V, TA = 25 °C,

UFBGA73 package

compliant with IEC 61967-2

0.1 MHz to 30 MHz

dBµV

30 MHz to 130 MHz

130 MHz to 1 GHz

1 GHz to 2 GHz

EMI level

Table 69. ESD absolute maximum ratings

Symbol

Ratings

Conditions

Class

Maximum value(1) Unit

VESD(HBM)

Electrostatic discharge voltage

(human body model)

TA = +25 °C, conforming to

ANSI/ESDA/JEDEC JS-001

2000

VESD(CDM)

Electrostatic discharge voltage

(charge device model)

TA = +25 °C, conforming to

ANSI/ESD STM5.3.1 JS-002

C2a

500

1. Guaranteed by characterization results.

Table 70. Electrical sensitivities

Symbol

Parameter

Conditions

Class

Static latch-up class

TA = +105 °C conforming to JESD78A

Level A

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