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PCIMX6DP7AVT2AB Datenblatt(PDF) 122 Page - NXP Semiconductors |
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PCIMX6DP7AVT2AB Datenblatt(HTML) 122 Page - NXP Semiconductors |
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122 / 166 page ![]() i.MX 6DualPlus/6QuadPlus Automotive Applications Processors, Rev. 3, 11/2018 122 NXP Semiconductors Electrical Characteristics 4.12.17.1.1 SATA PHY Transmitter Characteristics Table 77 provides specifications for SATA PHY transmitter characteristics. 4.12.17.1.2 SATA PHY Receiver Characteristics Table 78 provides specifications for SATA PHY receiver characteristics. 4.12.17.2 SATA_REXT Reference Resistor Connection The impedance calibration process requires connection of reference resistor 191 Ω. 1% precision resistor on SATA_REXT pad to ground. Resistor calibration consists of learning which state of the internal Resistor Calibration register causes an internal, digitally trimmed calibration resistor to best match the impedance applied to the SATA_REXT pin. The calibration register value is then supplied to all Tx and Rx termination resistors. During the calibration process (for a few tens of microseconds), up to 0.3 mW can be dissipated in the external SATA_REXT resistor. At other times, no power is dissipated by the SATA_REXT resistor. 4.12.18 SCAN JTAG Controller (SJC) Timing Parameters Figure 84 depicts the SJC test clock input timing. Figure 85 depicts the SJC boundary scan timing. Figure 86 depicts the SJC test access port. Figure 87 depicts the JTAG_TRST_B timing. Signal parameters are listed in Table 79. Figure 84. Test Clock Input Timing Diagram Table 77. SATA PHY Transmitter Characteristics Parameters Symbol Min Typ Max Unit Transmit common mode voltage VCTM 0.4 — 0.6 V Transmitter pre-emphasis accuracy (measured change in de-emphasized bit) —–0.5 — 0.5 dB Table 78. SATA PHY Receiver Characteristics Parameters Symbol Min Typ Max Unit Minimum Rx eye height (differential peak-to-peak) VMIN_RX_EYE_HEIGHT 175 — — mV Tolerance PPM –400 — 400 ppm JTAG_TCK (Input) VM VM VIH VIL SJ1 SJ2 SJ2 SJ3 SJ3 |
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