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SCIMX6DP5AVT2AB Datenblatt(PDF) 107 Page - NXP Semiconductors

Teilenummer SCIMX6DP5AVT2AB
Bauteilbeschribung  i.MX 6DualPlus/6QuadPlus Automotive Applications Processors
PDF  166 Pages
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Hersteller  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
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Electrical Characteristics
i.MX 6DualPlus/6QuadPlus Automotive Applications Processors, Rev. 3, 11/2018
NXP Semiconductors
107
4.12.11 LVDS Display Bridge (LDB) Module Parameters
The LVDS interface complies with TIA/EIA 644-A standard. For more details, see TIA/EIA STANDARD
644-A, “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits.”
4.12.12 MIPI D-PHY Timing Parameters
This section describes MIPI D-PHY electrical specifications, compliant with MIPI CSI-2 version 1.0,
D-PHY specification Rev. 1.0 (for MIPI sensor port x4 lanes) and MIPI DSI Version 1.01, and D-PHY
specification Rev. 1.0 (and also DPI version 2.0, DBI version 2.0, DSC version 1.0a at protocol layer) (for
MIPI display port x2 lanes).
4.12.12.1 Electrical and Timing Information
Table 67. LVDS Display Bridge (LDB) Electrical Specification
Parameter
Symbol
Test Condition
Min
Max
Units
Differential Voltage Output Voltage
VOD
100
Ω Differential load
250
450
mV
Output Voltage High
Voh
100
Ω differential load
(0 V Diff—Output High Voltage static)
1.25
1.6
V
Output Voltage Low
Vol
100
Ω differential load
(0 V Diff—Output Low Voltage static)
0.9
1.25
V
Offset Static Voltage
VOS
Two 49.9
Ω resistors in series between N-P
terminal, with output in either Zero or One state, the
voltage measured between the 2 resistors.
1.15
1.375
V
VOS Differential
VOSDIFF Difference in VOS between a One and a Zero state
-50
50
mV
Output short-circuited to GND
ISA ISB
With the output common shorted to GND
-24
24
mA
VT Full Load Test
VTLoad
100
Ω Differential load with a 3.74 kΩ load between
GND and I/O supply voltage
247
454
mV
Table 68. Electrical and Timing Information
Symbol
Parameters
Test Conditions
Min
Typ
Max
Unit
Input DC Specifications—Apply to DSI_CLK_P/_N and DSI_DATA_P/_N Inputs
VI
Input signal voltage range
Transient voltage range is limited from -300
mV to 1600 mV
-50
—
1350
mV
VLEAK
Input leakage current
VGNDSH(min) = VI = VGNDSH(max) +
VOH(absmax)
Lane module in LP Receive Mode
-10
—
10
mA
VGNDSH
Ground Shift
—
-50
—
50
mV
VOH(absmax)
Maximum transient output
voltage level
——
—
1.45
V
tvoh(absmax)
Maximum transient time
above VOH(absmax)
——
—
20
ns



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