PCIMX6DP7AVT2AB datasheet(113/168 Pages) NXP

113 / 168 page

Electrical Characteristics

i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018

NXP Semiconductors

113

4.12.12.9 Low-Power Receiver Timing

Figure 72. Input Glitch Rejection of Low-Power Receivers

4.12.13 HSI Host Controller Timing Parameters

This section describes the timing parameters of the HSI Host Controller which are compliant with

High-Speed Synchronous Serial Interface (HSI) Physical Layer specification version 1.01.

4.12.13.1 Synchronous Data Flow

Figure 73. Synchronized Data Flow READY Signal Timing (Frame and Stream Transmission)

4.12.13.2 Pipelined Data Flow

Figure 74. Pipelined Data Flow READY Signal Timing (Frame Transmission Mode)

2*TLPX

TMIN-RX

eSPIKE

Input

Output

VIH

VIL

N-bits Frame

First bit of

frame

NomBit

Last bit of

frame

First bit of

frame

Last bit of

frame

DATA

FLAG

READY

Receiver has

detected the start

of the Frame

Receiver has captured

and stored a complete

Frame

N-bits Frame

Last bit of

frame

DATA

FLAG

N-bits Frame

First bit of

frame

NomBit

Last bit of

frame

First bit of

frame

READY

A Ready can change

B Ready shall not

change to zero

Last bit of

frame

C. Ready can change

D. Ready shall

maintain zero of if

receiver does not

have free space

Ready

can

change

F. Ready

shall

maintain

its value

G. Ready

can change

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