PCIMX6DP6AVT2AB datasheet(129/168 Pages) NXP

129 / 168 page

Electrical Characteristics

i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018

NXP Semiconductors

129

NOTE

•

All the timings for the SSI are given for a non-inverted serial clock

polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have

been inverted, all the timing remains valid by inverting the clock signal

AUDx_TXC/AUDx_RXC and/or the frame sync

AUDx_TXFS/AUDx_RXFS shown in the tables and in the figures.

•

All timings are on Audiomux Pads when SSI is being used for data

transfer.

•

AUDx_TXC and AUDx_RXC refer to the Transmit and Receive

sections of the SSI.

•

The terms, WL and BL, refer to Word Length (WL) and Bit Length(BL).

•

For internal Frame Sync operation using external clock, the frame sync

timing is same as that of transmit data (for example, during AC97 mode

of operation).

Oversampling Clock Operation

SS47

Oversampling clock period

15.04

—

SS48

Oversampling clock high period

6.0

—

SS49

Oversampling clock rise time

—

3.0

SS50

Oversampling clock low period

6.0

—

SS51

Oversampling clock fall time

—

3.0

Table 83. SSI Receiver Timing with Internal Clock (continued)

Parameter

Min

Max

Unit

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