PCIMX6DP6AVT2AB datasheet(114/160 Pages) NXP

114 / 160 page

i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products, Rev. 3, 11/2018

114

NXP Semiconductors

Electrical Characteristics

4.12.13.9 DATA and FLAG Signal Timing

Figure 78. DATA and FLAG Signal Timing

4.12.14 PCIe PHY Parameters

The PCIe interface complies with PCIe specification Gen2 x1 lane and supports the PCI Express 1.1/2.0

standard.

4.12.14.1 PCIE_REXT Reference Resistor Connection

The impedance calibration process requires connection of reference resistor 200

Ω. 1% precision resistor

on PCIE_REXT pads to ground. It is used for termination impedance calibration.

4.12.15 Pulse Width Modulator (PWM) Timing Parameters

This section describes the electrical information of the PWM. The PWM can be programmed to select one

of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before

being input to the counter. The output is available at the pulse-width modulator output (PWMO) external

pin.

Figure 79 depicts the timing of the PWM, and Table 67 lists the PWM timing parameters.

Figure 79. PWM Timing

Table 67. PWM Output Timing Parameters

Parameter

Min

Max

Unit

—

PWM Module Clock Frequency

ipg_clk

MHz

PWM output pulse width high

—

PWM output pulse width low

—

DATA

(TX)

FLAG

(TX)

DATA

(RX)

FLAG

(RX)

50%

80%

20%

80%

EdgeSepTx

TxToRxSkew

EdgeSepRx

Bit

Rise

Fall

Note1

Note2

PWMn_OUT

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