D301 datasheet(284/416 Pages) MICROCHIP

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PIC24FJ256GA705 FAMILY

DS30010118D-page 284

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bit 8

G2D1N: Gate 2 Data Source 1 Negated Enable bit

1 = The Data Source 1 inverted signal is enabled for Gate 2

0 = The Data Source 1 inverted signal is disabled for Gate 2

bit 7

G1D4T: Gate 1 Data Source 4 True Enable bit

1 = The Data Source 4 signal is enabled for Gate 1

0 = The Data Source 4 signal is disabled for Gate 1

bit 6

G1D4N: Gate 1 Data Source 4 Negated Enable bit

1 = The Data Source 4 inverted signal is enabled for Gate 1

0 = The Data Source 4 inverted signal is disabled for Gate 1

bit 5

G1D3T: Gate 1 Data Source 3 True Enable bit

1 = The Data Source 3 signal is enabled for Gate 1

0 = The Data Source 3 signal is disabled for Gate 1

bit 4

G1D3N: Gate 1 Data Source 3 Negated Enable bit

1 = The Data Source 3 inverted signal is enabled for Gate 1

0 = The Data Source 3 inverted signal is disabled for Gate 1

bit 3

G1D2T: Gate 1 Data Source 2 True Enable bit

1 = The Data Source 2 signal is enabled for Gate 1

0 = The Data Source 2 signal is disabled for Gate 1

bit 2

G1D2N: Gate 1 Data Source 2 Negated Enable bit

1 = The Data Source 2 inverted signal is enabled for Gate 1

0 = The Data Source 2 inverted signal is disabled for Gate 1

bit 1

G1D1T: Gate 1 Data Source 1 True Enable bit

1 = The Data Source 1 signal is enabled for Gate 1

0 = The Data Source 1 signal is disabled for Gate 1

bit 0

G1D1N: Gate 1 Data Source 1 Negated Enable bit

1 = The Data Source 1 inverted signal is enabled for Gate 1

0 = The Data Source 1 inverted signal is disabled for Gate 1

CLCxGLSL: CLCx GATE LOGIC INPUT SELECT LOW REGISTER (CONTINUED)

D301 Datenblatt(PDF) 284 Page - Microchip Technology