8

ATmega640/V-1280/V-1281/V-2560/V-2561/V [SUMMARY]

2549QS–AVR–02/2014

2.3.6

Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buf-

fers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are

externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a

reset condition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the ATmega640/1280/1281/2560/2561 as listed on

page 80.

2.3.7

Port E (PE7..PE0)

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buf-

fers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are

externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a

reset condition becomes active, even if the clock is not running.

Port E also serves the functions of various special features of the ATmega640/1280/1281/2560/2561 as listed on

page 82.

2.3.8

Port F (PF7..PF0)

Port F serves as analog inputs to the A/D Converter.

Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal

pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both

high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not

running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be

activated even if a reset occurs.

Port F also serves the functions of the JTAG interface.

2.3.9

Port G (PG5..PG0)

Port G is a 6-bit I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have sym-

metrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally

pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset con-

dition becomes active, even if the clock is not running.

Port G also serves the functions of various special features of the ATmega640/1280/1281/2560/2561 as listed on

page 86.

2.3.10

Port H (PH7..PH0)

Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port H output buf-

fers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port H pins that are

externally pulled low will source current if the pull-up resistors are activated. The Port H pins are tri-stated when a

reset condition becomes active, even if the clock is not running.

Port H also serves the functions of various special features of the ATmega640/1280/2560 as listed on page 88.

2.3.11

Port J (PJ7..PJ0)

Port J is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port J output buffers

have symmetrical drive characteristics with both high sink and source capability. As inputs, Port J pins that are

externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a

reset condition becomes active, even if the clock is not running. Port J also serves the functions of various special

features of the ATmega640/1280/2560 as listed on page 90.