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DRA821U2...ALM Datenblatt(PDF) 143 Page - Texas Instruments

Teilenummer DRA821U2...ALM
Bauteilbeschribung  DRA821 Jacinto™ Processors
PDF  252 Pages
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DRA821U2...ALM Datenblatt(HTML) 143 Page - Texas Instruments

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7.9.4.2 Output Clocks
The device provides several system clock outputs. Summary of these output clocks are as follows:
• MCU_CLKOUT0
– Reference clock output for Ethernet PHYs (50 MHz or 25 MHz)
• MCU_SYSCLKOUT0
– SYSCLK0 of WKUP_PLLCTRL0 is divided by 6 and then sent out of the device as a LVCMOS clock signal
(MCU_SYSCLKOUT0). This signal can be used to test if the main chip clock is functioning or not.
• MCU_OBSCLK0
– On the clock output MCU_OBSCLK0, oscillators and PLLs clocks can be observed for tests and debug.
• SYSCLKOUT0
– SYSCLK0 from the MAIN_PLL controller is divided by 6 and then sent out of the device as a LVCMOS
clock signal (SYSCLKOUT0). This signal can be used to test if the main chip clock is functioning or not.
• CLKOUT
– Reference clock output
• OBSCLK[2:0]
– On the clock output OBSCLK0, oscillators and PLLs clocks can be observed for tests and debug.
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DRA821U-Q1
SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022
Copyright © 2022 Texas Instruments Incorporated
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