DRA821U2...ALM datasheet(156/252 Pages) TI

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PCB implementation. TI strongly recommends all designs to follow the TI LPDDR4 EVM PCB layout exactly in every detail (routing,

spacing, vias/backdrill, PCB material, etc.) in order to achieve the full specified clock frequency. Refer to the Jacinto 7 DDR Board

Design and Layout Guidelines for details.

DDR0_CKP

DDR0_CKN

Figure 7-49. DDRSS Memory Interface Clock Timing

For more information, see DDR Subsystem (DDRSS) section in Memory Controllers chapter in the device TRM.

7.9.5.5 ECAP

The supported features by the device ECAP are:

• 32-bit time base counter

• 4-event time-stamp registers (each 32 bits)

• Independent edge polarity selection for up to four sequenced time-stamp capture events

• Interrupt capabilities on any of the four capture events

• Input capture signal pre-scaling (from 1 to 16)

• Support of different capture modes (single shot capture, continuous mode capture, absolute timestamp

capture or difference mode time-stamp capture)

Table 7-33 represents ECAP timing conditions.

Table 7-33. ECAP Timing Conditions

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

Input Conditions

tSR

Input slew rate

V/ns

Output Conditions

CLOAD

Output load capacitance

Section 7.9.5.5.1 and Section 7.9.5.5.2 present timing and switching characteristics for ECAP (see Figure 7-50

and Figure 7-51).

7.9.5.5.1 Timing Requirements for ECAP

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

CAP1

tw(CAP)

Pulse duration, CAP (asynchronous)

2 + 2P

(1)

P = sysclk period in ns

CAP

CAP1

EPERIPHERALS_TIMNG_01

Figure 7-50. ECAP Input Timings

DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

www.ti.com

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