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DRA821U2...ALM Datenblatt(PDF) 206 Page - Texas Instruments

Teilenummer DRA821U2...ALM
Bauteilbeschribung  DRA821 Jacinto™ Processors
PDF  252 Pages
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DRA821U2...ALM Datenblatt(HTML) 206 Page - Texas Instruments

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Table 7-69. MMCSD1 Timing Requirements – UHS-I SDR12 Mode (continued)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
SDR124
th(clkH-dV)
Hold time, MMC[x]_DAT[3:0] valid after MMC[x]_CLK rising edge
1.67
ns
MMC[ ]_CMD
x
MMC
DAT
[ ]_
[3:0]
x
SDR121
SDR122
SDR123
SDR124
MMC[ ]_CLK
x
Figure 7-95. MMCSD1 – UHS-I SDR12 – Receive Mode
Table 7-70. MMCSD1 Switching Characteristics – UHS-I SDR12 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
fop(clk)
Operating frequency, MMC[x]_CLK
25
MHz
SDR125
tc(clk)
Cycle time, MMC[x]_CLK
40
ns
SDR126
tw(clkH)
Pulse duration, MMC[x]_CLK high
18.7
ns
SDR127
tw(clkL)
Pulse duration, MMC[x]_CLK low
18.7
ns
SDR128
td(clkH-cmdV)
Delay time, MMC[x]_CLK rising edge to MMC[x]_CMD transition
1.2
13.55
ns
SDR129
td(clkH-dV)
Delay time, MMC[x]_CLK rising edge to MMC[x]_DAT[3:0] transition
1.2
13.55
ns
MMC[ ]_CLK
x
MMC
CMD
[ ]_
x
MMC
DAT
[ ]_
[3:0]
x
SDR125
SDR127
SDR126
SDR128
SDR129
SDR128
SDR129
Figure 7-96. MMCSD1 – UHS-I SDR12 – Transmit Mode
7.9.5.16.2.4 UHS–I SDR25 Mode
Table 7-71 and Table 7-72 present timing requirements and switching characteristics for MMCSDi – UHS-I
SDR25 Mode (see Figure 7-97 and Figure 7-98).
Table 7-71. MMCSD1 Timing Requirements – UHS-I SDR25 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
SDR251
tsu(cmdV-clkH)
Setup time, MMC[x]_CMD valid before MMC[x]_CLK rising edge
2.1
ns
SDR252
th(clkH-cmdV)
Hold time, MMC[x]_CMD valid after MMC[x]_CLK rising edge
1.67
ns
SDR253
tsu(dV-clkH)
Setup time, MMC[x]_DAT[3:0] valid before MMC[x]_CLK rising edge
2.1
ns
SDR254
th(clkH-dV)
Hold time, MMC[x]_DAT[3:0] valid after MMC[x]_CLK rising edge
1.67
ns
MMC[ ]_CLK
x
MMC[ ]_CMD
x
MMC
DAT
[ ]_
[3:0]
x
SDR251
SDR252
SDR253
SDR254
Figure 7-97. MMCSD1 – UHS-I SDR25 – Receive Mode
DRA821U-Q1
SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022
www.ti.com
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