AT83SND1CXXX-ROTIL datasheet(156/212 Pages) ATMEL

156 / 212 page

156

4109J–8051–10/06

AT8xC51SND1C

Reset Value = 0001 0100b

Note:

1. When the SPI is disabled, SCK outputs high level.

Table 123. SPSTA Register

SPSTA (S:C4h) – SPI Status Register

Reset Value = 00000 0000b

Table 124. SPDAT Register

SPDAT (S:C5h) – Synchronous Serial Data Register

Reset Value = XXXX XXXXb

1 - 0

SPR1:0

SPI Rate Bits 0 and 1

Refer to Table 121 for bit rate description.

7654

3210

SPIF

WCOL

MODF

----

Bit

Number

Bit

Mnemonic

Description

SPIF

SPI Interrupt Flag

Set by hardware when an 8-bit shift is completed.

Cleared by hardware when reading or writing SPDAT after reading SPSTA.

6WCOL

Write Collision Flag

Set by hardware to indicate that a collision has been detected.

Cleared by hardware to indicate that no collision has been detected.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

4MODF

Mode Fault

Set by hardware to indicate that the SS pin is at an appropriate level.

Cleared by hardware to indicate that the SS pin is at an inappropriate level.

3 - 0

Reserved

The value read from these bits is indeterminate. Do not set these bits.

7654

3210

SPD7

SPD6SPD5SPD4SPD3SPD2SPD1

SPD0

Bit

Number

Bit

Mnemonic

Description

7 - 0

SPD7:0

Synchronous Serial Data.

Bit

Number

Bit

Mnemonic

Description

AT83SND1CXXX-ROTIL Datenblatt(PDF) 156 Page - ATMEL Corporation

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