TMP86FS49AIUG datasheet(171/296 Pages) TOSHIBA

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Page 155

TMP86FS49AIUG

13.9 Status Flag

13.9.1 Parity Error

When parity determined using the receive data bits differs from the received parity bit, the parity error flag

UART2SR<PERR> is set to “1”. The UART2SR<PERR> is cleared to “0” when the RD2BUF is read after

reading the UART2SR.

Figure 13-5 Generation of Parity Error

13.9.2 Framing Error

When “0” is sampled as the stop bit in the receive data, framing error flag UART2SR<FERR> is set to “1”.

The UART2SR<FERR> is cleared to “0” when the RD2BUF is read after reading the UART2SR.

Figure 13-6 Generation of Framing Error

13.9.3 Overrun Error

When all bits in the next data are received while unread data are still in RD2BUF, overrun error flag

UART2SR<OERR> is set to “1”. In this case, the receive data is discarded; data in RD2BUF are not affected.

The UART2SR<OERR> is cleared to “0” when the RD2BUF is read after reading the UART2SR.

Parity

Stop

Shift register

pxxxx0*

1pxxxx0

xxxx0**

RXD2 pin

UART2SR<PERR>

INTRXD2 interrupt

After reading UART2SR then

RD2BUF clears PERR.

Final bit

Stop

Shift register

xxxx0*

0xxxx0

xxx0**

RXD2 pin

UART2SR<FERR>

INTRXD2 interrupt

After reading UART2SR then

RD2BUF clears FERR.

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