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KSZ9567R Datenblatt(PDF) 185 Page - Microchip Technology |
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KSZ9567R Datenblatt(HTML) 185 Page - Microchip Technology |
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185 / 233 page ![]() 2022 Microchip Technology Inc. and its subsidiaries DS00002329E-page 185 KSZ9567R 5.2.11.8 Port PTP Egress Timestamp for PDelay_Resp High Word Register 5.2.11.9 Port PTP Egress Timestamp for PDelay_Resp Low Word Register 5.2.11.10 Port PTP Timestamp Interrupt Status Register Address: 0xNC10 - 0xNC11 Port N: 1-7 Size: 16 bits Bits Description Type Default 15:0 PTP Port N Egress Timestamp for Pdelay_Resp in Nanoseconds (PDLY_TS[31:16]) This field contains the Port N egress timestamp high-word value for the Pde- lay_Resp frame in nanoseconds. RO 0x0000 Address: 0xNC12 - 0xNC13 Port N: 1-7 Size: 16 bits Bits Description Type Default 15:0 PTP Port N Egress Timestamp for Pdelay_Resp in Nanoseconds (PDLY_TS[15:0]) This field contains the Port N egress timestamp low-word value for the Pde- lay_Resp frame in nanoseconds. RO 0x0000 Address: 0xNC14 - 0xNC15 Port N: 1-7 Size: 16 bits Bits Description Type Default 15 Port N Egress Timestamp for Sync Frame Interrupt Status (TS_SYNC_INT_STATUS) When this bit is set to 1, it indicates that the egress timestamp is available from Port N for the Sync frame. This bit is logical OR’ed together with the rest of the bits in this register and the output is shown as the PTP Interrupt Status bit in the Port Interrupt Status Register. R/W1C 0b 14 Port N Egress Timestamp for Pdelay_Req and Delay_Req Frames Interrupt Status (TS_PDLY_REQ_INT_STATUS) When this bit is set to 1, it indicates that the egress timestamp is available from Port N for the Pdelay_Req and Delay_Req frames. This bit is logical OR’ed together with the rest of the bits in this register and the output is shown as the PTP Interrupt Status bit in the Port Interrupt Status Register. R/W1C 0b 13 Port N Egress Timestamp for Pdelay_Resp Frame Interrupt Status (TS_PDLY_RESP_INT_STATUS) When this bit is set to 1, it indicates that the egress timestamp is available from Port N for the Pdelay_Resp frame. This bit is logical OR’ed together with the rest of the bits in this register and the output is shown as the PTP Interrupt Status bit in the Port Interrupt Status Register. R/W1C 0b 12:0 RESERVED RO 0x000 |
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