STM32H523VCU6TR datasheet(161/228 Pages) STMICROELECTRONICS

161 / 228 page

DS14540 Rev 1

161/228

STM32H523xx

Electrical characteristics

197

Figure 34. OCTOSPI timing diagram - DTR mode

VODr(CLK

)

(5)

CLK, NCLK crossing level on

CLK rising edge

VDD = 1.8 V

1000

1080

VODf(CLK

)

(5)

CLK, NCLK crossing level on

CLK falling edge

VDD = 1.8 V

930

1040

tw(CS)

Chip select high time

3 * t(CLK)

tv(DQ)

Data input valid time

tv(DS)

Data strobe input valid time

th(DS)

Data strobe input hold time

tv(RWDS) Data strobe output valid time

3 * t(CLK)

tsr(DQ),

tsf(DQ)

Data input setup time

-0.5

thr(DQ),

thf(DQ)

Data input hold time

tvr(OUT)

tvf(OUT)

Data output valid time

DHQC = 0

2.5

3.5

DHQC = 1, all prescaler

values (except 0)

t(CLK)/4

+ 0.5

t(CLK)/4 + 1

thr(OUT)

thf(OUT)

Data output hold time

DHQC = 0

1.5

DHQC = 1, all prescaler

values (except 0)

t(CLK)/4 - 1

1. Evaluated by characterization - Not tested in production.

2. Delay block activated.

3. Maximum frequency value are given for a maximum RWDS to DQ skew of ± 1.0 ns.

4. DHQC must be set to reach the mentioned frequency.

5. PF10/PB5, PB4/PB5 and PA3/PB5 are recommended to be in line with crossing specification.

Table 84. OCTOSPI characteristics in DTR mode (with DQS) / hyperbus(1)(2) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

MSv36879V4

Data output

Clock

Data input

t(CLK)

tw(CLKH)

tw(CLKL)

tr(CLK)

tf(CLK)

tsf(IN) thf(IN)

tvf(OUT)

thr(OUT)

tvr(OUT)

thf(OUT)

tsr(IN) thr(IN)

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