AM263P4 datasheet(126/168 Pages) TI2

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6.11.5.12.2.2.2.1 OSPI DLL Delay Mapping for PHY DDR Timing Modes

MODE

OSPI_PHY_CONFIGURATION_REG BIT

FIELD

DELAY VALUE

Transmit

3.3V

PHY_CONFIG_TX_DLL_DELAY_FLD

0x17

Receive

3.3V, DQS

PHY_CONFIG_RX_DLL_DELAY_FLD

0xA

3.3V, External Board Loopback

PHY_CONFIG_RX_DLL_DELAY_FLD

0x34

All other modes

PHY_CONFIG_RX_DLL_DELAY_FLD

0x0

6.11.5.12.2.2.2.2 OSPI Timing Requirements - PHY DDR Mode

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

O15

tsu(D-LBCLK)

Setup time, OSPI0_D[7:0] valid

before active OSPI0_DQS edge

3.3V, DDR with

External Board

Loopback

O15

tsu(D-LBCLK)

Setup time, OSPI0_D[7:0] valid

before active OSPI0_DQS edge

3.3V, DDR with

DQS

–0.86

O16

th(LBTCLK-D)

Hold time, OSPI0_D[7:0] valid

after active OSPI0_DQS edge

3.3V, DDR with

External Board

Loopback

4.7

O16

th(LBTCLK-D)

Hold time, OSPI0_D[7:0] valid

after active OSPI0_DQS edge

3.3V, DDR with

DQS

–0.95

tO16t

O15

OSPI_DQS

OSPI_D[i:0]

Figure 6-37. OSPI0 Timing Requirements – PHY DDR with External Board Loopback or DQS

6.11.5.12.2.2.2.3 OSPI Switching Characteristics - PHY DDR Mode

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

tc(CLK)

Cycle time, OSPI0_CLK

tw(CLKL)

Pulse duration, OSPI0_CLK low

0.475P(1) - 0.3

tw(CLKH)

Pulse duration, OSPI0_CLK high

0.475P(1) - 0.3

td(CSn-CLK)

Delay time, OSPI0_CSn[1:0] active edge

to OSPI0_CLK rising edge

0.475P(1) - (0.975

× M(2) × R(4))

0.525P(1) - (1.025

× M(2) × R(4)) + 7

td(CLK-CSn)

Delay time, OSPI0_CLK rising edge to

OSPI0_CSn[1:0] inactive edge

0.475P(1) + (0.975

× N(3) × R(4)) - 7

0.525P(1) + (1.025

× N(3) × R(4))

td(CLK-D)

Delay time, OSPI0_CLK active edge to

OSPI0_D[7:0] transition

3.3V

–6.35

–1.16

(1)

P = OSPI0_CLK cycle time = SCLK period in ns

(2)

M = OSPI_DEV_DELAY_REG[D_INIT_FLD]

(3)

N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]

(4)

R = REFCLK cycle time in ns

AM263P4, AM263P2, AM263P4-Q1, AM263P2-Q1

SPRSP81D – OCTOBER 2023 – REVISED MAY 2025

www.ti.com

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