RZSLASHT2M datasheet(119/128 Pages) RENESAS

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Table 2.47

Debug interface timing

Parameter

Symbol

Min.

Max.

Unit

Reference

figure

TCK cycle time

With an ICE connected

tTCKcyc

30*1

—

Figure 2.96

For use in BSCAN

—

TCK high pulse width

tTCKH

0.4

0.6

tTCKcyc

TCK low pulse width

tTCKL

0.4

0.6

tTCKcyc

TDI setup time

tTDIS

—

Figure 2.97

Output load:

30 pF

TDI hold time

tTDIH

—

TMS/SWDIO setup time

tTMSS

—

TMS/SWDIO hold time

tTMSH

—

SWDIO delay time

tSWDO

—

TDO delay time

With an ICE connected

tTDOD

—

For use in BSCAN

—

Capture register setup time

tCAPTS

—

Figure 2.98

Capture register hold time

tCAPTH

—

Update register delay time

tUPDATED

—

Trace clock cycle

tTCYC

—

Figure 2.99

Output load:

15 pF

Trace data delay

time

Trace clock: P18_6

tTDT

-2.3

3.3

Trace clock: P17_4

-2.5

3.0

Trace clock: P22_2

-1.0

4.2

Note 1. This value is the minimum cycle time for the normal operation of internal circuits.

The actual cycle time should be determined in consideration of the TCK capture edge timing and cable length of the connected ICE.

tTCKcyc

tTCKH

tTCKL

TCK

VIH

VIL

1/2 VCC33

VIH

Figure 2.96

TCK input timing

RZ/T2M Datasheet

2. Electrical Characteristics

R01DS0383EJ0130 Rev.1.30

Mar 13, 2026

Page 119 of 128

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