HD6417618 datasheet(184/646 Pages) RENESAS

Teilenummer	HD6417618

Bauteilbeschribung	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

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Section 7 Bus State Controller (BSC)

Rev. 6.00 Jun. 12, 2007 Page 152 of 610

REJ09B0131-0600

7.5.4

Extension of Chip Select (

CSn) Assertion Period

The number of cycles from

CSn assertion to RD and WEn (BEn) assertion can be specified by

setting bits SW1 and SW0 in CSnWCR. The number of cycles from

RD and WEn (BEn) negation

CSn negation can be specified by setting bits HW1 and HW0. Therefore, a flexible interface to

an external device can be obtained. Figure 7.10 shows an example. A Th cycle and a Tf cycle are

added before and after a normal cycle, respectively. In these cycles,

RD and WEn (BEn) are not

asserted, while other signals are asserted. The data output is prolonged to the Tf cycle, and this

prolongation is useful for devices with slow writing operations.

CKIO

A25 to A0

CSn

RD/

D15 to D0

WEn(BEn)

Read

Write

Figure 7.10 Example of Timing when

CSn Assertion Period is Extended

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