HD6417618A datasheet(374/646 Pages) RENESAS

374 / 646 page

Section 14 Serial Communication Interface with FIFO (SCIF)

Rev. 6.00 Jun. 12, 2007 Page 342 of 610

REJ09B0131-0600

Bit

Bit Name

Initial

value

R/W

Description

BRK

R/(W)* Break Detection

Indicates that a break signal has been detected in

receive data.

0: No break signal received

[Clearing conditions]

• BRK is cleared to 0 when the chip is a power-on

reset

• BRK is cleared to 0 when software reads BRK

after it has been set to 1, then writes 0 to BRK

1: Break signal received*

[Setting condition]

• BRK is set to 1 when data including a framing

error is received, and a framing error occurs with

space 0 in the subsequent receive data

Note: * When a break is detected, transfer of the

receive data (H'00) to SCFRDR stops after

detection. When the break ends and the

receive signal becomes mark 1, the transfer

of receive data resumes.

FER

Framing Error

Indicates a framing error in the data read from the

next receive FIFO data register (SCFRDR) in

asynchronous mode.

0: No receive framing error occurred in the next data

read from SCFRDR

[Clearing conditions]

• FER is cleared to 0 when the chip undergoes a

power-on reset

• FER is cleared to 0 when no framing error is

present in the next data read from SCFRDR

1: A receive framing error occurred in the next data

read from SCFRDR.

[Setting condition]

• FER is set to 1 when a framing error is present in

the next data read from SCFRDR

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