HD6417618A datasheet(245/646 Pages) RENESAS

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Section 9 Watchdog Timer (WDT)

Rev. 6.00 Jun. 12, 2007 Page 213 of 610

REJ09B0131-0600

9.3.2

Changing Frequency

To change the multiplication ratio of PLL circuit 1, use the WDT. When changing the frequency

only by switching the divider, do not use the WDT.

1. Before changing the frequency, always clear the TME bit in WTCSR to 0. When the TME bit

is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows.

2. Set the type of count clock used in the CKS2 to CKS0 bits in WTCSR and the initial values for

the counter in WTCNT. These values should ensure that the time till count overflow is longer

than the clock oscillation settling time.

3. When bits STC2 to STC0 in the frequency control register (FRQCR) is written, the processor

stops temporarily. The WDT starts counting.

4. When the WDT count overflows, the CPG resumes supplying the clock and the processor

resumes operation. The WOVF flag in WTCSR is not set when this happens.

5. WTCNT stops at the value of H'00.

6. Before changing WTCNT after the execution of the frequency change instruction, always

confirm that the value of WTCNT is H'00 by reading WTCNT.

9.3.3

Using Watchdog Timer Mode

1. Set the WT/IT bit in WTCSR to 1, set the type of count clock in bits CKS2 to CKS0, and set

the initial value of the counter in WTCNT.

2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode.

3. While operating in watchdog timer mode, rewrite the counter periodically to H'00 to prevent

the counter from overflowing.

4. When the counter overflows, the WDT sets the WOVF flag in WTCSR to 1 and generates a

power-on reset. WTCNT then resumes counting.

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