HD64F2149YV datasheet(333/1075 Pages) RENESAS

Teilenummer	HD64F2149YV

Bauteilbeschribung	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

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Section 10 14-Bit PWM Timer

Rev. 3.00 Jan 18, 2006 page 305 of 1044

REJ09B0280-0300

Table 10.4

Settings and Operation (Examples when

φφφφ = 10 MHz)

Fixed DADR Bits

Bit Data

CKS

Resolution

(µs)

CFS

Base

Cycle

(µs)

Conversion

Cycle

(µs)

L (if OS = 0)

H (if OS = 1)

Precision

(Bits)

321 0

Conversion

Cycle*

(µs)

1638.4

0 0

409.6

6.4

1638.4

1. Always low (or high)

(DADR = H'0001 to

H'03FD)

2. (Data value)

× T

(DADR = H'0401 to

H'FFFD)

0 0 0 0

102.4

1638.4

0 0

409.6

00.1

25.6

1638.4

1. Always low (or high)

(DADR = H'0003 to

H'00FF)

2. (Data value)

× T

(DADR = H'0103 to

H'FFFF)

0 0 0 0

102.4

3276.8

0 0

819.2

12.8

3276.8

1. Always low (or high)

(DADR = H'0001 to

H'03FD)

2. (Data value)

× T

(DADR = H'0401 to

H'FFFD)

0 0 0 0

204.8

3276.8

0 0

819.2

10.2

51.2

3276.8

1. Always low (or high)

(DADR = H'0003 to

H'00FF)

2. (Data value)

× T

(DADR = H'0103 to

H'FFFF)

0 0 0 0

204.8

Note:

This column indicates the conversion cycle when specific DADR bits are fixed.

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