HD64F2149YV datasheet(351/1075 Pages) RENESAS

351 / 1075 page

Section 11 16-Bit Free-Running Timer

Rev. 3.00 Jan 18, 2006 page 323 of 1044

REJ09B0280-0300

Bit 2—Buffer Enable B (BUFEB): Selects whether ICRD is to be used as a buffer register for

ICRB.

Bit 2

BUFEB

Description

ICRD is not used as a buffer register for input capture B

(Initial value)

ICRD is used as a buffer register for input capture B

Bits 1 and 0—Clock Select (CKS1, CKS0): Select external clock input or one of three internal

clock sources for the FRC. External clock pulses are counted on the rising edge of signals input to

the external clock input pin (FTCI).

Bit 1

Bit 0

CKS1

CKS0

Description

φ/2 internal clock source

(Initial value)

φ/8 internal clock source

φ/32 internal clock source

External clock source (rising edge)

11.2.9

Timer Output Compare Control Register (TOCR)

Bit

Initial value

Read/Write

ICRDMS

R/W

OCRAMS

R/W

ICRS

R/W

OCRS

OEA

OLVLB

R/W

OEB

R/W

OLVLA

R/W

TOCR is an 8-bit readable/writable register that enables output from the output compare pins,

selects the output levels, switches access between output compare registers A and B, controls the

ICRD and OCRA operating mode, and switches access to input capture registers A to C.

TOCR is initialized to H'00 by a reset and in hardware standby mode.

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