HD64F2149YV datasheet(369/1075 Pages) RENESAS

Teilenummer	HD64F2149YV

Bauteilbeschribung	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

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Section 11 16-Bit Free-Running Timer

Rev. 3.00 Jan 18, 2006 page 341 of 1044

REJ09B0280-0300

Contention between OCR Write and Compare-Match: If a compare-match occurs during the

state after an OCRA or OCRB write cycle, the write takes priority and the compare-match signal

is inhibited.

Figure 11.20 shows this type of contention.

If automatic addition of OCRAR/OCRAF to OCRA is selected, and a compare-match occurs in

the cycle following the OCRA, OCRAR and OCRAF write cycle, the OCRA, OCRAR and

OCRAF write takes priority and the compare-match signal is inhibited. Consequently, the result of

the automatic addition is not written to OCRA.

Figure 11.21 shows this timing

OCRA or OCRB write cycle

Address

Internal write signal

FRC

OCR

Write data

OCR address

N + 1

Compare-match

signal

Prohibited

Figure 11.20 Contention between OCR Write and Compare-Match

(When Automatic Addition Function Is Not Used)

HD64F2149YV Datenblatt(PDF) 369 Page - Renesas Technology Corp