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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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HD64F2149YV Datenblatt(PDF) 316 Page - Renesas Technology Corp |
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HD64F2149YV Datenblatt(HTML) 316 Page - Renesas Technology Corp |
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316 / 1075 page  Section 9 8-Bit PWM Timers Rev. 3.00 Jan 18, 2006 page 288 of 1044 REJ09B0280-0300 9.2.5 Peripheral Clock Select Register (PCSR) Bit Initial value Read/Write 7 — 0 — 6 — 0 — 5 — 0 — 4 — 0 — 3 — 0 — 0 — 0 — 2 PWCKB 0 R/W 1 PWCKA 0 R/W PCSR is an 8-bit readable/writable register that selects the PWM timer input clock. PCSR is initialized to H'00 by a reset, and in hardware standby mode. Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 0. Bits 2 and 1—PWM Clock Select (PWCKB, PWCKA): Together with bits PWCKE and PWCKS in PWSL, these bits select the internal clock input to TCNT in the PWM timer. For details, see section 9.2.1, PWM Register Select (PWSL). Bit 0—Reserved: Do not set this bit to 1. 9.2.6 Port 1 Data Direction Register (P1DDR) Bit Initial value Read/Write 7 P17DDR 0 W 6 P16DDR 0 W 5 P15DDR 0 W 4 P14DDR 0 W 3 P13DDR 0 W 0 P10DDR 0 W 2 P12DDR 0 W 1 P11DDR 0 W P1DDR is an 8-bit write-only register that specifies the input/output direction and PWM output for each pin of port 1 on a bit-by-bit basis. Port 1 pins are multiplexed with pins PW0 to PW7. The bit corresponding to a pin to be used for PWM output should be set to 1. For details on P1DDR, see section 8.2, Port 1. |
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