H8SXSLASH1663R datasheet(507/1504 Pages) RENESAS

Teilenummer	H8SX/1663R

Bauteilbeschribung	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

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Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 475 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

value

R/W

Description

SAT1

SAT0

R/W

Source Address Update Mode 1 and 0

These bits specify incrementing/decrementing of the

transfer source address (EDSAR). When the transfer

source is not specified in EDSAR in single address

mode, the specification by these bits is ignored.

00: Fixed

01: Offset added

10: Incremented (+1, +2, or +4 according to the data

access size)

11: Decremented (

−1, −2, or −4 according to the data

access size)

19, 18



All 0

Reserved

They are always read as 0 and cannot be modified.

DAT1

DAT0

R/W

Destination Address Update Mode 1 and 0

These bits specify incrementing/decrementing of the

transfer destination address (EDDAR). When the

transfer source is not specified in EDDAR in single

address mode, the specification by these bits is

ignored.

00: Fixed

01: Offset added

10: Incremented (+1, +2, or +4 according to the data

access size)

11: Decremented (

−1, −2, or −4 according to the data

access size)

H8SX/1663R Datenblatt(PDF) 507 Page - Renesas Technology Corp

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