H8SXSLASH1663R datasheet(702/1504 Pages) RENESAS

702 / 1504 page

Section 13 I/O Ports

Rev. 2.00 Sep. 24, 2008 Page 670 of 1468

REJ09B0412-0200

13.3.5

Port Function Control Register 6 (PFCR6)

PFCR6 selects the TPU clock input pin.

Bit

Bit Name

Initial Value

R/W



R/W

LHWROE

R/W



R/W



TCLKS

R/W



R/W



R/W



R/W

Bit

Bit Name

Initial

Value

R/W

Description



R/W

Reserved

This bit is always read as 1. The write value should

always be 1.

LHWROE

R/W

LHWR Output Enable

Enables/disables

LHWR output (valid in external

extended mode).

0: Specifies pin PA4 as I/O port

1: Specifies pin PA4 as

LHWR output pin



R/W

Reserved

This bit is always read as 1. The write value should

always be 1.



Reserved

This is a read-only bit and cannot be modified.

TCLKS

R/W

TPU External Clock Input Pin Select

Selects the TPU external clock input pins.

0: Specifies pins P32, P33, P35, and P37 as external

clock input pins.

1: Specifies pins P14 to P17 as external clock input

pins.

2, 1



All 0

R/W

Reserved

These bits are always read as 0. The write value should

always be 0.

ADTRG0S 0

R/W

ADTRG0S Input Pin Select

Selects the external trigger input pins of A/D converter.

0: Specifies pin P13 as

ADTRG0-A input pin.

1: Specifies pin PB6 as

ADTRG0-B input pin.

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