H8SXSLASH1663R datasheet(715/1504 Pages) RENESAS

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Section 14 16-Bit Timer Pulse Unit (TPU)

Rev. 2.00 Sep. 24, 2008 Page 683 of 1468

REJ09B0412-0200

Section 14 16-Bit Timer Pulse Unit (TPU)

This LSI has two on-chip 16-bit timer pulse units (TPU), unit 0 and unit 1, each comprises six

channels. Therefore, this LSI includes twelve channels.

Functions of unit 0 and unit 1 are shown in table 14.1 and table 14.2 respectively. Block diagrams

of unit 0 and unit 1 are shown in figure 14.1 and figure 14.2 respectively.

This section explains unit 0. This explanation is common to unit 1.

14.1

Features

• Maximum 16-pulse input/output

• Selection of eight counter input clocks for each channel

• The following operations can be set for each channel:

 Waveform output at compare match

 Input capture function

 Counter clear operation

 Synchronous operations:

• Multiple timer counters (TCNT) can be written to simultaneously

• Simultaneous clearing by compare match and input capture possible

• Simultaneous input/output for registers possible by counter synchronous operation

• Maximum of 15-phase PWM output possible by combination with synchronous

operation

• Buffer operation settable for channels 0 and 3

• Phase counting mode settable independently for each of channels 1, 2, 4, and 5

• Cascaded operation

• Fast access via internal 16-bit bus

• 26 interrupt sources

• Automatic transfer of register data

• Programmable pulse generator (PPG) output trigger can be generated (unit 0 only)

• Conversion start trigger for the A/D converter can be generated (unit 0 only)

• Module stop state can be set

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