H8SXSLASH1663R datasheet(734/1504 Pages) RENESAS

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Section 14 16-Bit Timer Pulse Unit (TPU)

Rev. 2.00 Sep. 24, 2008 Page 702 of 1468

REJ09B0412-0200

14.3.2

Timer Mode Register (TMDR)

TMDR sets the operating mode for each channel. The TPU has six TMDR registers, one for each

channel. TMDR register settings should be made only while TCNT operation is stopped.



BFB

R/W

BFA

R/W

MD3

R/W

MD2

R/W

MD1

R/W

MD0

R/W

Bit

Bit Name

Initial Value

R/W

Bit

Bit Name

Initial

Value

R/W

Description

7, 6



All 1



Reserved

These bits are always read as 1 and cannot be modified.

BFB

R/W

Buffer Operation B

Specifies whether TGRB is to normally operate, or TGRB

and TGRD are to be used together for buffer operation.

When TGRD is used as a buffer register, TGRD input

capture/output compare is not generated.

In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is

reserved. It is always read as 0 and cannot be modified.

0: TGRB operates normally

1: TGRB and TGRD used together for buffer operation

BFA

R/W

Buffer Operation A

Specifies whether TGRA is to normally operate, or TGRA

and TGRC are to be used together for buffer operation.

When TGRC is used as a buffer register, TGRC input

capture/output compare is not generated.

In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is

reserved. It is always read as 0 and cannot be modified.

0: TGRA operates normally

1: TGRA and TGRC used together for buffer operation

MD3

MD2

MD1

MD0

R/W

Modes 3 to 0

Set the timer operating mode.

MD3 is a reserved bit. The write value should always be

0. See table 14.13 for details.

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