H8SXSLASH1663R datasheet(866/1504 Pages) RENESAS

Teilenummer	H8SX/1663R

Bauteilbeschribung	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

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Section 16 8-Bit Timers (TMR)

Rev. 2.00 Sep. 24, 2008 Page 834 of 1468

REJ09B0412-0200

16.5.2

Timing of CMFA and CMFB Setting at Compare Match

The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the

TCOR and TCNT values match. The compare match signal is generated at the last state in which

the match is true, just before the timer counter is updated. Therefore, when the TCOR and TCNT

values match, the compare match signal is not generated until the next TCNT clock input. Figure

16.9 shows this timing.

TCNT

N + 1

TCOR

Compare match

signal

CMF

Figure 16.9 Timing of CMF Setting at Compare Match

16.5.3

Timing of Timer Output at Compare Match

When a compare match signal is generated, the timer output changes as specified by the bits OS3

to OS0 in TCSR. Figure 16.10 shows the timing when the timer output is toggled by the compare

match A signal.

Compare match A

signal

Timer output pin

Figure 16.10 Timing of Toggled Timer Output at Compare Match A

H8SX/1663R Datenblatt(PDF) 866 Page - Renesas Technology Corp