H8SXSLASH1663R datasheet(1081/1504 Pages) RENESAS

1081 / 1504 page

Section 21 I

2C Bus Interface 2 (IIC2)

Rev. 2.00 Sep. 24, 2008 Page 1049 of 1468

REJ09B0412-0200

21.3.7

2C Bus Transmit Data Register (ICDRT)

ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects a

space in the I

2C bus shift register, it transfers the transmit data which has been written to ICDRT

to ICDRS and starts transmitting data. If the next data is written to ICDRT during transmitting

data to ICDRS, continuous transmission is possible.

Bit

Bit Name

Initial Value

R/W

21.3.8

2C Bus Receive Data Register (ICDRR)

ICDRR is an 8-bit read-only register that stores the receive data. When one byte of data has been

received, ICDRR transfers the receive data from ICDRS to ICDRR and the next data can be

received. ICDRR is a receive-only register; therefore, this register cannot be written to by the

CPU.

Bit

Bit Name

Initial Value

R/W

21.3.9

2C Bus Shift Register (ICDRS)

ICDRS is an 8-bit register that is used to transmit/receive data. In transmission, data is transferred

from ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred

from ICDRS to ICDRR after one by of data is received. This register cannot be read from or

written to by the CPU.

Bit

Bit Name

Initial Value

R/W

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