H8SXSLASH1663R datasheet(253/1504 Pages) RENESAS

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Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 221 of 1468

REJ09B0412-0200

9.4

Multi-Clock Function and Number of Access Cycles

The internal functions of this LSI operate synchronously with the system clock (I

φ), the peripheral

module clock (P

φ), or the external bus clock (Bφ). Table 9.1 shows the synchronization clock and

their corresponding functions.

Table 9.1

Synchronization Clocks and Their Corresponding Functions

Synchronization Clock

Function Name

MCU operating mode

Interrupt controller

Bus controller

CPU

DTC

DMAC

EXDMAC

Internal memory

Clock pulse generator

Power down control

I/O ports

TPU

PPG

TMR

WDT

SCI

A/D

D/A

IIC2

USB

External bus interface

The frequency of each synchronization clock (I

φ, Pφ, and Bφ) is specified by the system clock

control register (SCKCR) independently. For further details, see section 27, Clock Pulse

Generator.

There will be cases when P

φ and Bφ are equal to Iφ and when Pφ and Bφ are different from Iφ

according to the SCKCR specifications. In any case, access cycles for internal peripheral functions

and external space is performed synchronously with P

φ and Bφ, respectively.

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