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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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H8SX/1663R Datenblatt(PDF) 277 Page - Renesas Technology Corp |
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H8SX/1663R Datenblatt(HTML) 277 Page - Renesas Technology Corp |
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277 / 1504 page  Section 9 Bus Controller (BSC) Rev. 2.00 Sep. 24, 2008 Page 245 of 1468 REJ09B0412-0200 9.6.3 Basic Timing This section describes the basic timing when the data is specified as big endian. (1) 16-Bit 2-State Access Space Figures 9.15 to 9.17 show the bus timing of 16-bit 2-state access space. When accessing 16-bit access space, the upper byte data bus (D15 to D8) is used for even addresses access, and the lower byte data bus (D7 to D0) is used for odd addresses. No wait cycles can be inserted. 1. n = 0 to 7 2. When RDNn = 0 3. When DKC and EDKC = 0 Valid Invalid Valid T 1 T 2 Address CSn AS RD D15 to D8 D7 to D0 D15 to D8 D7 to D0 LHWR LLWR Read Write Notes: High level High-Z B φ Bus cycle BS RD/ WR DACK or EDACK Figure 9.15 16-Bit 2-State Access Space Bus Timing (Byte Access for Even Address) |
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