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R8C/15 Datenblatt(PDF) 153 Page - Renesas Technology Corp |
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R8C/15 Datenblatt(HTML) 153 Page - Renesas Technology Corp |
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153 / 277 page ![]() R8C/14 Group, R8C/15 Group 15. Clock Synchronous Serial I/O with Chip Select (SSU) Rev.2.10 Jan 19, 2006 Page 141 of 253 REJ09B0164-0210 Figure 15.1 Block Diagram of SSU SSMR Register Transmit / Receive Control Circuit SSCRL Register SSCRH Register SSER Register SSSR Register SSMR2 Register SSTDR Register SSTRSR Register SSRDR Register Selector Multiplexer SSO SSI SCS SSCK Interrupt Requests (TXI, TEI, RXI, OEI and CEI) Internal Clock Generation Circuit f1 Internal Clock(f1/i) i = 4, 8, 16, 32, 64, 128 and 256 |
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