M38044F2HKP datasheet(329/387 Pages) RENESAS

329 / 387 page

3-39

REJ09B0212-0100Z

Rev.1.00

Jan 14, 2005

3804 Group (Spec.H)

APPENDIX

3.3 Notes on use

3.3.15 Quartz-crystal oscillator

When using the quartz-crystal oscillator of high frequency, such as 16 MHz etc., it may be necessary to

select a specific oscillator with the specification demanded.

3.3.16 Notes on restarting oscillation

(1)

Restarting oscillation

Usually, when the MCU stops the clock oscillation by STP instruction and the STP instruction has

been released by an external interrupt source, the fixed values of Timer 1 and Prescaler 12 (Timer

1 = “0116”, Prescaler 12 = “FF16”) are automatically reloaded in order for the oscillation to stabilize.

The user can inhibit the automatic setting by writing “1” to bit 0 of MISRG (address 001016).

However, by setting this bit to “1”, the previous values, set just before the STP instruction was

executed, will remain in Timer 1 and Prescaler 12. Therefore, you will need to set an appropriate

value to each register, in accordance with the oscillation stabilizing time, before executing the STP

instruction.

q Reason

Oscillation will restart when an external interrupt is received. However, internal clock

φ is supplied

to the CPU only when Timer 1 starts to underflow. This ensures time for the clock oscillation using

the ceramic resonators to be stabilized.

3.3.17 Notes on using stop mode

sRegister setting

Since values of the prescaler 12 and Timer 1 are automatically reloaded when returning from the

stop mode, set them again, respectively. (When the oscillation stabilizing time set after STP

instruction released bit is “0”)

sClock restoration

After restoration from the stop mode to the normal mode by an interrupt request, the contents of

the CPU mode register previous to the STP instruction execution are retained. Accordingly, if both

main clock and sub clock were oscillating before execution of the STP instruction, the oscillation

of both clocks is resumed at restoration.

In the above case, when the main clock side is set as a system clock, the oscillation stabilizing

time until the timer 1 underflow is reserved at restoration from the stop mode.

When the oscillation stabilizing time set after STP instruction released bit is “0”, the time for 512

counts of the count source become the oscillation stabilizing time. When the oscillation stabilizing

time set after STP instruction released bit is “1”, an arbitrarily count value set to the prescaler 12

and the timer 1 become the oscillation stabilizing time.

At this time, note that the oscillation on the sub clock side may not be stabilized even after the

lapse of the oscillation stabilizing time of the main clock side.

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