M38044F2HKP datasheet(363/387 Pages) RENESAS

363 / 387 page

3-73

REJ09B0212-0100Z

Rev.1.00

Jan 14, 2005

3804 Group (Spec.H)

APPENDIX

3.5 Control registers

Fig. 3.5.38 Structure of CPU mode register

CPU mode register

b7 b6 b5 b4 b3 b2 b1 b0

CPU mode register

(CPUM: address 003B16)

00 : Single-chip mode

01 :

10 :

Not available

11 :

Name

Functions

At reset R W

0 : 0 page

1 : 1 page

0: Oscillating

1: Stopped

Processor mode

bits

Stack page

selection bit

Port Xc switch bit

Fix this bit to “1”.

Main clock (XIN-

XOUT) stop bit

Main clock division

ratio selection bits

b1 b0

b7 b6

0 0:

φ=f(XIN)/2

(high-speed mode)

0 1:

φ=f(XIN)/8

(middle-speed mode)

1 0:

φ=f(XCIN)/2

(low-speed mode)

1 1: not available

0: I/O port function

(stop oscillating)

1: XCIN-XCOUT oscillation

function

Fig. 3.5.37 Structure of Interrupt edge selection register

Interrupt edge selection register

b7 b6 b5 b4 b3 b2 b1 b0

Interrupt edge selection register

(INTEDGE: address 003A16)

0: Falling edge active

1: Rising edge active

Name

Functions

At reset R W

INT0 active edge

selection bit

0: Falling edge active

1: Rising edge active

INT1 active edge

selection bit

0: Falling edge active

1: Rising edge active

INT2 active edge

selection bit

0: Falling edge active

1: Rising edge active

INT3 active edge

selection bit

0: Falling edge active

1: Rising edge active

INT4 active edge

selection bit

INT0, INT4 interrupt

switch bit

Nothing is arranged for this bit. This is a write

disabled bit. When this bit is read out, the

contents are “0”.

Nothing is arranged for this bit. This is a write

disabled bit. When this bit is read out, the

contents are “0”.

0: INT00, INT40 interrupt

1: INT01, INT41 interrupt

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