M38044F2HKP datasheet(236/387 Pages) RENESAS

Teilenummer	M38044F2HKP

Bauteilbeschribung	8-BIT CISC SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES

PDF	387 Pages

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Hersteller	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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APPLICATION

2.5 Multi-master I2C-BUS interface

Rev.1.00 Jan 14, 2004

REJ09B0212-0100Z

3804 Group (Spec.H)

➄ Transmission of upper data

Confirm correct completion of the upper data transmission. The master returns the NACK toward

the transmitted second-byte data, the upper data. Accordingly, confirm that the last receive bit

(LRB bit; bit 0 of address 001316) is “1”.

After that, write dummy data to the I2C data shift register and wait for the interrupt of STOP

condition.

Fig. 2.5.33 Transmission process of upper data

End

S0 (address 001116)

← 111111112

Error end

0 (ACK)

LRB (address 001316), bit 0 ?

1 (NACK)

PIN (address 001316), bit 4 ?

1 (STOP condition)

0 (upper data transmission completed)

S1 (address 001316)

← 000100002

Note: Use the branch bit instruction to check bus busy.

• Judgment of bus hold

• ACK confirmation

• Slave receive mode set

• Dummy data write to I2C data shift register

M38044F2HKP Datenblatt(PDF) 236 Page - Renesas Technology Corp