M38044F2HKP datasheet(323/387 Pages) RENESAS

323 / 387 page

3-33

REJ09B0212-0100Z

Rev.1.00

Jan 14, 2005

3804 Group (Spec.H)

APPENDIX

3.3 Notes on use

(2)

Notes when selecting clock asynchronous serial I/O

➀ Stop of transmission operation

Clear the transmit enable bit to “0” (transmit disabled). The transmission operation does not stop

by clearing the serial I/Oi enable bit (i = 1, 3) to “0”.

q Reason

This is the same as ➀ in (1).

➁ Stop of receive operation

Clear the receive enable bit to “0” (receive disabled).

➂ Stop of transmit/receive operation

Only transmission operation is stopped.

Clear the transmit enable bit to “0” (transmit disabled). The transmission operation does not stop

by clearing the serial I/Oi enable bit (i = 1, 3) to “0”.

q Reason

This is the same as ➀ in (1).

Only receive operation is stopped.

Clear the receive enable bit to “0” (receive disabled).

(3)

SRDYi (i = 1, 3) output of reception side

When signals are output from the SRDYi pin on the reception side by using an external clock in the

clock synchronous serial I/O mode, set all of the receive enable bit, the SRDYi output enable bit, and

the transmit enable bit to “1” (transmit enabled).

(4)

Setting serial I/Oi (i = 1, 3) control register again

Set the serial I/Oi control register again after the transmission and the reception circuits are reset

by clearing both the transmit enable bit and the receive enable bit to “0.”

Fig. 3.3.3 Sequence of setting serial I/Oi (i = 1, 3) control register again

(5)

Data transmission control with referring to transmit shift register completion flag

After the transmit data is written to the transmit buffer register, the transmit shift register completion flag

changes from “1” to “0” with a delay of 0.5 to 1.5 shift clocks. When data transmission is controlled with

referring to the flag after writing the data to the transmit buffer register, note the delay.

(6)

Transmission control when external clock is selected

When an external clock is used as the synchronous clock for data transmission, set the transmit

enable bit to “1” at “H” of the SCLKi (i = 1, 3) input level. Also, write the transmit data to the transmit

buffer register at “H” of the SCLKi input level.

Clear both the transmit enable

bit (TE) and the receive enable

bit (RE) to “0”

↓

Set the bits 0 to 3 and bit 6 of the

serial I/Oi control register

↓

Set both the transmit enable bit

(TE) and the receive enable bit

(RE), or one of them to “1”

Can be set with the

LDM instruction at

the same time

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