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M38046FDHKP Datenblatt(PDF) 344 Page - Renesas Technology Corp

Teilenummer M38046FDHKP
Bauteilbeschribung  8-BIT CISC SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES
PDF  387 Pages
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Hersteller  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M38046FDHKP Datenblatt(HTML) 344 Page - Renesas Technology Corp

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3-54
REJ09B0212-0100Z
Rev.1.00
Jan 14, 2005
3804 Group (Spec.H)
APPENDIX
3.5 Control registers
Fig. 3.5.7 Structure of I2C special mode status register
I2C special mode status register
b7 b6 b5 b4 b3 b2 b1 b0
I2C special mode status register
(S3: address 001216)
b
0
1
2
3
4
5
6
7
Name
0
Functions
At reset R W
0
0
0
1
0
0
0
Slave address 0
comparison flag
(AAS0)
0: Address disagreement
1: Address agreement
(Notes 1, 2)
Slave address 1
comparison flag
(AAS1)
0: Address disagreement
1: Address agreement
(Notes 1, 2)
Slave address 2
comparison flag
(AAS2)
0: SCL pin low hold
1: SCL pin low release
(Notes 1, 3)
SCL pin low hold 2
flag (PIN2)
STOP condition
flag (SPCF)
0: No detection
1: Detection (Notes 1, 4)
Notes 1: These bits and flags can be read out, but cannot be written.
2: These bits can be detected only when the data format selection bit
(ALS) of I2C control register is set to “0”.
3: This bit is initialized to “1” at reset, when the ACK interrupt control bit
is “0”, or when writing “1” to the SCL pin low hold 2 flag set bit.
4: This bit is initialized to “0” at reset, when the I2C-BUS interface
enable bit (ES0) is “0”, or when writing “1” to the STOP condition
flag clear bit.
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0: Address disagreement
1: Address agreement
(Notes 1, 2)
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are undefined.



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