M38046FDHKP datasheet(351/387 Pages) RENESAS

351 / 387 page

3-61

REJ09B0212-0100Z

Rev.1.00

Jan 14, 2005

3804 Group (Spec.H)

APPENDIX

3.5 Control registers

Fig. 3.5.16 Structure of UART1 control register

Fig. 3.5.17 Structure of Baud rate generator i

UART1 control register

b7 b6 b5 b4 b3 b2 b1 b0

UART1 control register

(UART1CON: address 001B16)

0: 8 bits

1: 7 bits

Character length

selection bit (CHAS)

Parity enable bit

(PARE)

Stop bit length

selection bit (STPS)

P45/TxD1 P-channel

output disable bit

(POFF)

Parity selection bit

(PARS)

Functions

Name

At reset R W

Nothing is arranged for these bits. These are

write disabled bits. When these bits are read

out, the contents are “1”.

0: Parity checking disabled

1: Parity checking enabled

0: Even parity

1: Odd parity

0: 1 stop bit

1: 2 stop bits

0: CMOS output

(in output mode)

1: N-channel open-drain

output (in output mode)

Baud rate generator i (i = 1, 3)

b7 b6 b5 b4 b3 b2 b1 b0

Baud rate generator i

(BRGi (i=1, 3): address 001C16, 002F16)

Undefined

At reset R W

Functions

Set a count value of baud rate generator.

Note: Write to this register while transmit/receive operation is stopped.

Undefined

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