AT89C5122DS-RDRUM datasheet(104/208 Pages) ATMEL

104 / 208 page

104

AT83R5122, AT8xC5122/23

4202F–SCR–07/2008

Bulk/Interrupt IN Transactions

in Ping-Pong Mode

Figure 57.

Bulk / Interrupt IN transactions in Ping-Pong mode

An endpoint will be first enabled and configured before being able to send Bulk or Inter-

rupt packets.

The firmware will fill the FIFO bank 0 with the data to be sent and set the TXRDY bit in

the UEPSTAX register to allow the USB controller to send the data stored in FIFO at the

next IN request concerning the endpoint. The FIFO banks are automatically switched,

and the firmware can immediately write into the endpoint FIFO bank 1.

When the IN packet concerning the bank 0 has been sent and acknowledged by the

Host, the TXCMPL bit is set by the USB controller. This triggers a USB interrupt if

enabled. The firmware will clear the TXCMPL bit before filling the endpoint FIFO bank 0

with new data. The FIFO banks are then automatically switched.

When the IN packet concerning the bank 1 has been sent and acknowledged by the

Host, the TXCMPL bit is set by the USB controller. This triggers a USB interrupt if

enabled. The firmware will clear the TXCMPL bit before filling the endpoint FIFO bank 1

with new data.

The bank switch is performed by the USB controller each time the TXRDY bit is set by

the firmware. Until the TXRDY bit has been set by the firmware for an endpoint bank,

the USB controller will answer a NAK handshake for each IN requests concerning this

bank.

Note that in the example above, the firmware clears the Transmit Complete bit (TXC-

MPL) before setting the Transmit Ready bit (TXRDY). This is done in order to avoid the

firmware to clear at the same time the TXCMPL bit for bank 0 and the bank 1.

The firmware will never write more bytes than supported by the endpoint FIFO.

DATA0 (n Bytes)

ACK

HOST

UFI

C51

Endpoint FIFO Bank 0 - Write Byte 1

NACK

TXCMPL

Endpoint FIFO Bank 0 - Write Byte 2

Endpoint FIFO Bank 0 - Write Byte n

Set TXRDY

Endpoint FIFO Bank 1 - Write Byte 1

Endpoint FIFO Bank 1 - Write Byte 2

Endpoint FIFO Bank 1 - Write Byte m

Set TXRDY

DATA1 (m Bytes)

ACK

Endpoint FIFO Bank 0 - Write Byte 1

Endpoint FIFO Bank 0 - Write Byte 2

Endpoint FIFO Bank 0 - Write Byte p

Set TXRDY

Clear TXCMPL

DATA0 (p Bytes)

ACK

TXCMPL

Clear TXCMPL

Endpoint FIFO Bank 1 - Write Byte 1

AT89C5122DS-RDRUM Datenblatt(PDF) 104 Page - ATMEL Corporation

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