AM79C975VCW datasheet(254/304 Pages) AMD

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254

Am79C973/Am79C975

P R E L I M INARY

since the frequency of the acknowledgment frames is

very low.

Once the receive activity has ended, the Am79C975

controller will set the MRX_DONE bit in the Interrupt

Status register. The MIRQ pin will be asserted, if the

global interrupt enable bit MIRQEN in the Command

(MRX_DONEM) is cleared to 0 (default state). Once

MIRQ is asserted, the host can read the MRX_DONE

bit in the Interrupt register to determine that the inter-

rupt was caused by the end of the reception. The read

of the Interrupt register will clear the MRX_DONE bit

and cause the deassertion of the MIRQ pin. The Inter-

rupt register also provides a global interrupt bit MIRQ

that is the OR of the MRX_DONE and MTX_DONE

bits.

Once the MRX_DONE bit indicates that the reception

of the acknowledgment frame has ended, the Receive

Status register provides the error status for the recep-

tion. Two error conditions are reported: Framing Error

and Frame Check Sequence Error. There is also an

error summary bit (MRX_ERR). The receive status bits

remain valid as long as the MRX_ENABLE bit is set to

0. The host has the option to discard an erroneous

frame by simply not reading the receive data and un-

protecting the Receive Data memory by setting the

MRX_ENABLE bit.

The host must read the Receive Message Length reg-

ister in order to determine the length of the frame. The

data from the Receive Data memory is read byte by

byte using one or multiple Block Read commands from

the Receive Data port. The command code of the Block

Read command must be set to 40, the address of the

Receive Data port. The Am79C975 controller will indi-

cate in the byte count field the number of bytes that will

follow. The byte count field will indicate 32 in all but the

last transaction in which the byte count field will indi-

cate the remaining bytes of the frame. The device is ca-

pable of transferring data beyond the 32 byte mark. If

the host does not assert NACK after the 32nd byte, the

Am79C975 controller will continue driving receive data

onto the MDATA line until the host asserts NACK. If the

master does not have enough buffer space for the in-

coming data, it can abort the data transfer after any

byte. The Am79C975 controller will start the next Block

Read command with the remaining data. The location

within the Receive Data memory from where the next

byte is read is controlled by the Receive Address regis-

ter. This register will come up cleared to 0 after

H_RESET. With every byte read the address register

will auto-increment. This allows a FIFO-type access to

the Receive Data memory and the host does not need

to keep track of the location he is reading from. In addi-

tion, MRX_ADR can be set to any address within the

Receive Data memory in order to read a specific loca-

tion or to start the receive data read from an arbitrary

address inside the Receive Data memory. Note, that

the byte count field in the Block Read command will

only reflect the correct amount of transfer data if the ac-

cess starts at Receive Data memory address 0. If

MRX_ADR is manually changed, the byte count field

should be ignored. The host must use the Receive

Message Length register (MRX_LEN) to determine the

length of the data read operation. Data will be unde-

fined, if the host reads further than the Receive Mes-

sage Length register is indicating.

The Receive Data memory will be protected from over-

writing by another frame, until the host enables the next

receive by setting the MRX_ENABLE bit the Receive

Status register. The operation will also clear the Re-

ceive Address register.

Loopback Operation

The SMIU provides a looback mode for diagnostic pur-

poses. If MLOOP in the Command register is set to 1,

the receive path is not being blocked while the device

is transmitting in half-duplex mode. Receive is never

blocked in full-duplex mode and MLOOP has no effect

in this mode.

For loopback operation, transmit data must be sent

back to the receiver. This is done at the transceiver by

either using an external loopback connector or by pro-

gramming the transceiver for loopback mode. The pro-

gramming must be done using the Am79C975 CSR/

BCR register interface. This limits the SMIU loopback

mode to a debug or manufacturing test environment.

User Accessible Registers

The Serial Management Interface Unit (SMIU) of the

Am79C975 controller provides four types of user ac-

cessible registers: device ID registers, node address

registers, device status registers and control and status

registers. Most registers are accessible via the Read

Byte and/or Write Byte commands. Only the access to

the Transmit and Receive Data port as well as to the

Receive Pattern RAM Data port is performed as a

Block Read or Block Write command. In all commands,

the command code is interpreted as the address of the

Device ID Registers

The following register allow the unique identification of

the Am79C975 device in a system.

SMIU Vendor ID Register 0 (MReg Address 0)

This register is a shadow register of the PCI Vendor ID

from the EEPROM.

Bit No.

Name and Description

7:0

MVENDOR_ID[7:0]

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