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ATMEGA256RFR2-ZU Datenblatt(PDF) 2 Page - ATMEL Corporation |
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ATMEGA256RFR2-ZU Datenblatt(HTML) 2 Page - ATMEL Corporation |
2 / 2 page A VR O N - CHIP D EBUG S YSTEM JT AGICE MK II © Atmel Corporation 2004. All rights reserved. Atmel® and combinations thereof, AVR®, AVR Studio®, are registered trademarks of Atmel. Other terms and product names may be trademarks of others. 2489D-AVR-02/04/ 0M Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 USA TEL: (1)(408) 441-0311 FAX: (1)(408) 487-2600 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL: (41) 26-426-5555 FAX: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong TEL: (852) 2721-9778 FAX: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL: (81) 3-3523-3551 FAX: (81) 3-3523-7581 Web Site http://www.atmel.com O rdering Information The JTAGICE is available from Atmel franchised distributors. The ordering code is ATJTAGICE2 The latest version of AVR Studio is available free of charge from Atmel web site: www.atmel.com The JTAGICE will automatically be upgraded by future AVR Studio releases to support future devices with JTAG support as they are released. Supported Devices JTAG ATmega16 ATmega162 ATmega169 ATmega32 ATmega329 ATmega3290 ATmega64 ATmega649 ATmega6490 ATmega128 ATmega1281 ATmega1280 ATmega128CAN11 ATmega256 ATmega2560 DebugWIRE ATtiny13 ATtiny2313 ATtiny25 ATtiny45 ATmega48 ATmega88 ATmega168 The JTAGICE mkII interface is integrated in AVR Studio, Atmel’s front-end tool for development on the AVR architecture. All phases of the AVR development can be done in this Integrated Development Environment. The JTAGICE mkII allows access to all the powerful features of the AVR microcon- troller. All AVR resources can be monitored: Flash memory, EEPROM memory, SRAM memory, Register File, Program Counter, Fuse and Lock Bits, and all I/O modules. The JTAGICE mkII also offers extensive On-chip Debug support for break conditions, including break on change of Program memory flow, Program memory Break Points on single address or address range, and Data memory Break Points on single address or address range. The debugWIRE uses the Reset line for electrical connection; hence the system designer does not have to sacrifice I/O capabilities to take full advantage of the On-Chip-Debug system. The JTAGICE mkII will automatically be upgraded by future AVR Studio releases to support future devices with JTAG and debugWIRE support as they are released. Note: Low voltage devices are also supported. |
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