8

Test Circuits

FIGURE 3. INTEGRAL AND DIFFERENTIAL NON-LINEARITY ERROR AND OFFSET VOLTAGE TEST CIRCUIT

FIGURE 4. MAXIMUM OPERATIONAL SPEED AND DIFFERENTIAL GAIN AND PHASE ERROR TEST CIRCUIT

FIGURE 5. DIGITAL OUTPUT CURRENT TEST CIRCUIT

-

HI5675

DUT

8

CLK (20MHz)

+

A<B

A>B

COMPARATOR

A8

A1

A0

B8

B1

B0

“0”

“1”

8

S1

S2

-V

+V

S1: ON IF A < B

S2: ON IF A > B

BUFFER

DVM

CONTROLLER

8

TO

111 • • • 10

000 • • • 00

TO

TO

SIGNAL

SOURCE

NTSC

SG

8

8

SCOPE

VECTOR

620

DG

ERROR RATE

SG

(CW)

AMP

HI5675

DUT

ECL

TTL

D/A

10-BIT

-5.2V

CLK

1

2

1

2

HPF

COUNTER

DP

620

-5.2V

ECL

TTL

-40

0

100

IRE

SYNC

BURST

0.6V

2.6V

40 IRE

MODULATION

0.6V

2.6V

HI20201

CLK

OE

GND

0.6V

2.6V

+

-

CLK

OE

GND

0.6V

2.6V

+

-

HI5675

HI5675

HI5675