MEC1322 datasheet(115/456 Pages) MICROCHIP

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 2014 - 2015 Microchip Technology Inc.

DS00001719D-page 115

MEC1322

9.5

Power, Clocks and Reset

This section defines the Power, Clock, and Reset parameters of the block.

9.5.1

POWER DOMAINS

9.5.2

CLOCK INPUTS

This block has no special clocking requirements. Host register accesses are synchronized to the host bus clock and EC

9.5.3

RESETS

9.6

Interrupts

This section defines the Interrupt Sources generated from this block.

9.7

Low Power Modes

The Embedded Memory Interface (EMI) automatically enters low power mode when no transaction target it.

TABLE 9-1:

POWER SOURCES

Name

Description

VCC1

The logic and registers implemented in this block reside on this single

power well.

TABLE 9-2:

RESET SIGNALS

Name

Description

VCC1_RESET

This reset signal resets all the logic and register in this block.

TABLE 9-3:

SYSTEM INTERRUPTS

Source

Description

Host Event

This interrupt source for the SIRQ logic is generated when any of the

EC_SWI bits are asserted and the corresponding EC_SWI_EN bits are

asserted as well.

This event is also asserted if the host writes the EC-to-HOST Mailbox

EC-to-Host

This interrupt source for the SIRQ logic is generated by the host writing

the EC-to-HOST Mailbox Register.

TABLE 9-4:

EC INTERRUPTS

Source

Description

Host-to-EC

Interrupt source for the Interrupt Aggregator, generated by the host writ-

ing the HOST-to-EC Mailbox Register.

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