UCC2974

UCC3974

SLUS485A – JULY 2001 – REVISED NOVEMBER 2001

11

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startup sequence

t0

t2

t1

t3

t4

LFD ENABLE

OPEN LAMP

DETECT ENABLE

OUTPUT ENABLE

DEVICE ENABLE

0.0

0.5

1.0

3.0

4.0

MODE

UDG–01026

Figure 5. Start-Up Sequence

Figure 5 describes what happens during a typical startup sequence. At t0, power is applied to the system. A

constant current source begins charging the external capacitor connected to the MODE pin. Until the voltage

on the MODE pin reaches 0.5 V (t1), the internal circuitry on the device is disabled and nothing happens at the

outputs. As the voltage crosses 0.5 V, the internal circuitry is powered up. When the voltage crosses 1 V at t2,

the outputs are enabled, allowing the buck stages to begin to charge up and to supply current to the royer stages.

During the period from t2 to t3, the open lamp detection circuitry is disabled, preventing a false trip of the open

lamp detector circuit when the lamp is trying to ignite for the first time. As a precaution against severe

overvoltage on the high-voltage secondary of the transformer, a clamp circuit is included in the UCC3974. The

function of the clamp circuit is to monitor the voltage on the BUCK pins and prevent that voltage to drop more

than 8.7-V below the input rail. This is accomplished by sourcing a current from the FB pin when the BUCK

voltage drops more than 8.7 V.

The magnitude of the current sourced from this pin is proportional to the excess drop of the BUCK voltage

beyond 8.7 V. The maximum current sourced from this pin is approximately 200

µA. Consequently, the

impedance at the FB pin affects the speed at which this clamp becomes effective. A small capacitor and large

resistors in the feedback network increases the effectiveness of this feature. From t3 onward, the open lamp

detector circuit is enabled. Each time the BUCK pin drops more than 7.8-V below VIN, a 4-bit counter is clocked.

If the counter reaches a count of 16 (4 bits) it declares an open lamp fault and shuts down the device. Resetting

the device requires a power cycle. The counter in the open lamp detector is an up/down counter. If the BUCK

pin only occasionally dips below the 7.8-V threshold, an open lamp condition is not declared since the counter

is clocked down on each cycle in which BUCK does not cross the 7.8-V threshold. At time t4, LFD is enabled.

Depending on the state of LFDSYNC when this threshold is crossed, DIM is either an analog input or a digital

one.