WM8281ECSSLASHR datasheet(101/392 Pages) CIRRUS

101 / 392 page

WM8281

Rev 4.0

101

The PWM sample rate (cycle time) is configured using the PWM_RATE register - see Table 23. Note

that sample rate conversion is required when linking the PWM generators to any signal chain that is

asynchronous and/or configured for a different sample rate.

The PWM generators are enabled using PWM1_ENA and PWM2_ENA respectively, as described in

Table 22.

Under default conditions (PWMn_OVD = 0), the duty cycle of the PWM generators is controlled by an

audio signal path; a 4-input mixer is associated with each PWM generator, as illustrated in Figure 37.

When the PWMn_OVD bit is set, the duty cycle of the respective PWM generator is set to a fixed

ratio; in this case, the duty cycle ratio is configurable using the PWMn_LVL registers.

The PWM generator clock frequency is selected using PWM_CLK_SEL. For best performance, this

set to a higher frequency than SYSCLK (if PWM_RATE<1000) or ASYNCCLK (if PWM_RATE

≥1000).

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R48 (0030h)

PWM Drive

10:8

PWM_CLK_SEL

[2:0]

000

PWM Clock Select

000 = 6.144MHz (5.6448MHz)

001 = 12.288MHz (11.2896MHz)

010 = 24.576MHz (22.5792MHz)

All other codes are Reserved

The frequencies in brackets apply for

44.1kHz-related sample rates only.

PWM_CLK_SEL controls the resolution

of the PWM generator; higher settings

correspond to higher resolution.

The PWM Clock must be less than or

equal to SYSCLK (if PWM_RATE<1000)

or less than or equal to ASYNCCLK (if

PWM_RATE>=1000).

PWM2_OVD

PWM2 Generator Override

0 = Disabled (PWM duty cycle is

controlled by audio source)

1 = Enabled (PWM duty cycle is

controlled by PWM2_LVL).

PWM1_OVD

PWM1 Generator Override

0 = Disabled (PWM1 duty cycle is

controlled by audio source)

1 = Enabled (PWM1 duty cycle is

controlled by PWM1_LVL).

PWM2_ENA

PWM2 Generator Enable

0 = Disabled

1 = Enabled

PWM1_ENA

PWM1 Generator Enable

0 = Disabled

1 = Enabled

R49 (0031h)

PWM Drive

9:0

PWM1_LVL [9:0]

100h

PWM1 Override Level

Sets the PWM1 duty cycle when

PWM1_OVD=1.

Coded as 2’s complement.

000h = 50% duty cycle

200h = 0% duty cycle

R50 (0032h)

PWM Drive

9:0

PWM2_LVL [9:0]

100h

PWM2 Override Level

Sets the PWM2 duty cycle when

PWM2_OVD=1.

Coded as 2’s complement.

000h = 50% duty cycle

200h = 0% duty cycle

Table 22 Pulse Width Modulation (PWM) Generator Control

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