WM8281ECSSLASHR datasheet(226/392 Pages) CIRRUS

226 / 392 page

WM8281

226

Rev 4.0

When a valid ‘Write Sequencer’ control event is detected, the respective control sequence will be

scheduled. See “Control Write Sequencer” for further details.

Note that the trigger status (_TRIG_STS) bits are latching fields. Care is required when resetting

these bits, to ensure the intended device behaviour - resetting the _TRIG_STS register(s) may cause

LDO1 (and DCVDD) to be disabled.

A valid clock (SYSCLK) must be enabled whenever a Control Write Sequence is scheduled.

If the JD1, GP5 or MICDET Clamp trigger status bits are associated with the Control Write Sequencer

(using the register bits in Table 85) and also configured as Wake-Up events (using the register bits in

Table 84), then the Boot Sequence must be programmed to configure and enable SYSCLK. (Note

that the default SYSCLK frequency must be used in this case.)

The Boot Sequence (see “Hardware Reset, Software Reset, Wake-Up, and Device ID”) is scheduled

as part of the Wake-Up transition, and provides the capability to configure SYSCLK (and other

Note that, if the Control Write Sequencer is triggered during normal operation, then SYSCLK will

typically be already available, and no additional requirements will apply.

To return to Sleep mode following a Wake-Up / Write Sequence, the last step of the control sequence

must be to write ‘1’ to the applicable trigger status bit(s). The _TRIG_STS bit(s) will be reset, LDO1

will be disabled, and the WM8281 will be in Sleep mode. (The LDO1_ENA bit must be set to 0, and

the LDOENA pin must not be asserted.)

To remain ‘On’ at the end of a Wake-up / Write Sequence, the control sequence must write ‘1’ to the

LDO1_ENA bit before resetting the trigger status bit(s). Alternatively, the host processor should assert

the LDOENA pin before resetting the trigger status bit(s).

When the Control Write Sequencer is triggered during normal operation, it can be programmed to

select the Sleep mod

e by writing ‘0’ to the LDO1_ENA bit. (The LDOENA pin must not be asserted.)

See “Charge Pumps, Regulators and Voltage Reference” for details of the LDO1_ENA control bit.

INTERRUPT CONTROL

An Interrupt Request (IRQ) event can be associated with the JD1, GP5 or MICDET Clamp signals.

Separate ‘mask’ bits are provided to enable IRQ events on the rising and/or falling edges of each

signal.

See “Interrupts” for further details.

WM8281ECS/R Datenblatt(PDF) 226 Page - Cirrus Logic