WM8281ECSSLASHR datasheet(236/392 Pages) CIRRUS

236 / 392 page

WM8281

236

Rev 4.0

DSP STATUS FLAG (DSP IRQn) OUTPUT

GPn_FN = 35h, 36h, 37h, 38h, 39h, 3A, 3Bh, 3Ch, 45h, 46h, 47h, 48h.

The WM8281 supports up to eight DSP Status flags as outputs from the DSP blocks. These are

configurable within the DSP to provide external indication of the required function(s). Status flags

indicating the DSPn RAM status (where ‘n’ is 1, 2, 3 or 4) are also supported. See “Digital Core” for

more details of the DSP blocks.

The DSP Status and DSP RAM Ready flags may be output directly on a GPIO pin by setting the

respective GPIO registers as described in “GPIO Control”. The DSP Status and DSP RAM Ready

outputs are described in Table 89.

The DSP Status flags are inputs to the Interrupt Controller circuit. An interrupt event is triggered on

the rising edge of the DSP Status (DSP_IRQn) flags or DSP RAM Ready flags. The associated

interrupt bits are latched once set; they can be polled at any time or used to control the IRQ signal.

See “Interrupts” for more details of the Interrupt event handling.

GPN_FN

DESCRIPTION

COMMENTS

35h

DSP Status (DSP_IRQ1)

External indication of DSP_IRQ1_STS

36h

DSP Status (DSP_IRQ2)

External indication of DSP_IRQ2_STS

37h

DSP Status (DSP_IRQ3)

External indication of DSP_IRQ3_STS

38h

DSP Status (DSP_IRQ4)

External indication of DSP_IRQ4_STS

39h

DSP Status (DSP_IRQ5)

External indication of DSP_IRQ5_STS

3Ah

DSP Status (DSP_IRQ6)

External indication of DSP_IRQ6_STS

3Bh

DSP Status (DSP_IRQ7)

External indication of DSP_IRQ7_STS

3Ch

DSP Status (DSP_IRQ8)

External indication of DSP_IRQ8_STS

45h

DSP1 RAM Ready

Indicates DSP1 RAM Ready status

46h

DSP2 RAM Ready

Indicates DSP2 RAM Ready status

47h

DSP3 RAM Ready

Indicates DSP3 RAM Ready status

48h

DSP4 RAM Ready

Indicates DSP4 RAM Ready status

Table 89 DSP Status and RAM Ready Indications

OPCLK AND OPCLK_ASYNC CLOCK OUTPUT

GPn_FN = 04h, 3Dh.

A clock output (OPCLK) derived from SYSCLK can be output on a GPIO pin. The OPCLK frequency

is controlled by OPCLK_DIV and OPCLK_SEL. The OPCLK output is enabled using the OPCLK_ENA

A clock output (OPCLK_ASYNC) derived from ASYNCCLK can be output on a GPIO pin. The

OPCLK_ASYNC frequency is controlled by OPCLK_ASYNC_DIV and OPCLK_ASYNC_SEL. The

OPCLK_ASYNC output is enabled using the OPCLK_ASYNC_ENA register

It is recommended to disable the clock output (OPCLK_ENA=0 or OPCLK_ASYNC_ENA=0) before

making any change to the respective OPCLK_DIV, OPCLK_SEL, OPCLK_ASYNC_DIV or

OPCLK_ASYNC_SEL registers.

The OPCLK or OPCLK_ASYNC Clock outputs can be output directly on a GPIO pin by setting the

respective GPIO registers as described in “GPIO Control”.

Note that the OPCLK source frequency cannot be higher than the SYSCLK frequency. The

OPCLK_ASYNC source frequency cannot be higher than the ASYNCCLK frequency. The maximum

output frequency supported for GPIO output is noted in the “Electrical Characteristics”.

ee “Clocking and Sample Rates” for more details of the system clocks (SYSCLK and ASYNCCLK).

WM8281ECS/R Datenblatt(PDF) 236 Page - Cirrus Logic

WM8281ECS/R Datenblatt(HTML) 236 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL